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ISL55110, ISL55111
Pin Configurations
ISL55110
(16 LD QFN)
TOP VIEW
ISL55111
(16 LD QFN)
TOP VIEW
VDD
ENABLE
PD
1
2
3
16
15
14
13
12 OB
11 GND
10 VH
VDD
ENABLE
PD
1
2
3
16
15
14
13
12 OB
GND
11
10 VH
IN-B
4
9
OA
IN-B
4
9
OA
5
6
7
8
5
6
7
8
ISL55110
(8 LD TSSOP)
TOP VIEW
ISL55111
(8 LD TSSOP)
TOP VIEW
VDD
PD
IN-B
1
2
3
8 OB
7 GND
6 VH
VDD
PD
IN-B
1
2
3
8 OB
7 GND
6 VH
IN-A
4
5
OA
IN-A
4
5
OA
Pin Descriptions
16 LD QFN
1
10
11
3
2
8 LD TSSOP
1
6
7
2
-
PIN
VDD
VH
GND
PD
ENABLE
FUNCTION
Logic Power.
Driver High Rail Supply.
Ground, Return for Both VH Rail and VDD Logic Supply.
Power-Down. Active Logic High Places Part in Power-Down Mode.
QFN Packages Only. When the ENABLE pin is low, the device will operate normally (outputs controlled
by the inputs). When the ENABLE pin is tied high, the output will be tri-stated. In other words, it will
act as if it is open or floating regardless of what is on the IN-x pins. This provides a High Speed HIZ
Logic Control of Driver Outputs.
5
4
4
3
IN-A
IN-B, INB
Logic Level Input that Drives OA to VH Rail or Ground. Not Inverted.
Logic Level Input that Drives OB to VH Rail or Ground. Not Inverted on ISL55110, Inverted on
ISL55111.
9
12
6 through 8,
5
8
-
OA
OB
NC
Driver Output Related to IN-A.
Driver Output Related to IN-B.
No Connect.
13 through 16
2
FN6228.6
August 8, 2013
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